The present invention relates, in general, to the field of integrated circuit logic circuits and devices. More particularly, the present invention relates to layout area efficient, high speed, dynamic multi-input exclusive OR (XOR) and exclusive NOR (XNOR) logic gate circuit designs of especial utility with respect to integrated circuit devices.
Error correction circuitry (ECC) and other types of logic functions that make use of parity require XOR and the XNOR logic gate functions. These XOR and XNOR gates are more difficult to implement with complementary metal oxide semiconductor (CMOS) technology than standard NAND and NOR logic gates, particularly when considering multi-input gates having more than two inputs. Conventional static three-input XOR circuits are generally slow and require many transistors. Representative implementations of various XOR logic gates are shown, for example, in U.S. Pat. No. 4,749,886 issued Jun. 7, 1988 for “Reduced Parallel Exclusive OR and Exclusive NOR Gate”, U.S. Pat. No. 4,888,499 issued Dec. 19, 1989 for “Three Input Exclusive OR-NOR Gate Circuit' and U.S. Pat. No. 5,936,427 issued Aug. 10, 1999 for “Three-Input Exclusive NOR Circuit”. Examples of conventional four-input XOR circuits are shown, for example, in U.S. Pat. No. 4,570,084 issued Feb. 11, 1986 for “Clocked Differential Cascode Voltage Switch Logic Systems” and U.S. Pat. No. 5,134,616 issued Jul. 28, 1996 for “Dynamic RAM with On-Chip ECC and Optimized Bit and Word Redundancy”. The larger number input XOR gates are important in order to reduce stages in wide-word ECC circuit blocks.